Coprocessors: Difference between revisions

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This page describes various instructions associated to coprocessors on the ARM chip.  
This page describes various instructions associated to coprocessors on the ARM chip. <ref>ARM,1176jzf-s: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301g/ch03s02s01.html; ARM,Cortex-A8: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344j/ch03s02s01.html</ref>


== CP15: System Control Coprocessor ==
== CP15: System Control Coprocessor ==
Only Opcode 0 is described in the ARM-ARM. To copy data from the coprocessor to the register <tt>rD</tt>, use the assembly
Most operations are done using opcode "0". To read data from the coprocessor to the register <tt>rD</tt>, use the assembly
  mcr p15, 0, <rD>, <cN>, c0, <opcode2>
  mcr p15, 0, <rD>, <cN>, <cM>, <opcode2>
  mrc p15, 0, <rS>, <cN>, c0, <opcode2>
To write data into coprocessor from <tt>rS</tt>, so
  mrc p15, 0, <rS>, <cN>, <cM>, <opcode2>


=== N=c0: ID codes ===
=== Notable usage ===
ID codes are used to obtain information about the chip, e.g. the vendor, the cache size, etc. These values are all, naturally, read-only (only <tt>mcr</tt> should be used).
In the iPhoneOS user-land, the most prominent use of CP15 is to provide thread-local storage via the "User read-only thread and process ID" register. For instance, in [[libSystem.dylib]], <tt>pthread_self()</tt> is implemented as
{| class="wikitable"
<source lang="asm">
_pthread_self:
mrc p15, 0, r0, c13, c0, 3
bx lr
</source>
 
=== Register allocation for Opcode 0 ===
 
{| class="wikitable sortable"
|-
! cN !! cM !! opcode2 !! Register !! Readable (mcr) !! Writable (mrc) !! Comments
|-
| c0 || c0 || 0 || Main ID || {{yes2}} Privileged || {{no}} || Contains vendor, architecture, part number, etc.<ref>http://infocenter.arm.com/help/topic/com.arm.doc.ddi0211h/I65012.html</ref>
|-
| c0 || c0 || 1 || Cache type || {{yes2}} Privileged || {{no}} || Size and architecture of cache.<ref>http://infocenter.arm.com/help/topic/com.arm.doc.ddi0211h/I67616.html</ref>
|-
| c0 || c0 || 2 || Tightly coupled memory (TCM) status || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c0 || 3 || Translation look-aside buffer (TLB) type || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c0 || 5 || Multiprocessor ID || {{yes2}} Privileged  || {{no}} || (Cortex only.)
|-
| c0 || c1 || 0 || Processor feature 0 || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c1 || 1 || Processor feature 1 || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c1 || 2 || Debug feature 0 || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c1 || 3 || Auxiliary feature 0 || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c1 || 4 || Memory model feature 0 || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c1 || 5 || Memory model feature 1 || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c1 || 6 || Memory model feature 2 || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c1 || 7 || Memory model feature 3 || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c2 || 0 || Instruction set features 0 || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c2 || 1 || Instruction set features 1 || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c2 || 2 || Instruction set features 2 || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c2 || 3 || Instruction set features 3 || {{yes2}} Privileged  || {{no}} ||
|-
| c0 || c2 || 4 || Instruction set features 4 || {{yes2}} Privileged  || {{no}} ||
|-
| c1 || c0 || 0 || Control || {{yes2}} Privileged || {{yes2}} Privileged || Controls whether MMU, cache, etc. are enabled or not.
|-
| c1 || c0 || 1 || Auxiliary control || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c1 || c0 || 2 || Coprocessor access control || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c1 || c1 || 0 || Secure configuration || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c1 || c1 || 1 || Secure debug enable || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
|-
! opcode2 !! Register || Comment
| c1 || c1 || 2 || Non-secure access control || {{yes2}} Privileged || {{yes2}} Privileged ||  
|-
|-
| 0 || Main ID register || Gives information of the vendor, architecture, part number and revision.
| c2 || c0 || 0 || Translation table base 0 (TTBR0) || {{yes2}} Privileged || {{yes2}} Privileged ||  
|-
|-
| 1 || Cache type register || Gives information of the cache type and size.
| c2 || c0 || 1 || Translation table base 1 (TTBR1) || {{yes2}} Privileged || {{yes2}} Privileged ||  
|-
|-
| 2 || Tightly Coupled Memory (TCM) type register ||  
| c2 || c0 || 2 || Translation table base control || {{yes2}} Privileged || {{yes2}} Privileged ||  
|-
|-
| 3 || TLB type register ||
| c3 || c0 || 0 || Domain access control || {{yes2}} Privileged || {{yes2}} Privileged ||  
|-
|-
| 4 || Memory Protection Unit (MPU) type register ||
| c5 || c0 || 0 || Data fault status (D-FSR) || {{yes2}} Privileged || {{yes2}} Privileged ||
|}
|-
 
| c5 || c0 || 1 || Instruction fault status (I-FSR) || {{yes2}} Privileged || {{yes2}} Privileged ||
=== N=c1: Control registers ===
|-
Configure for the cache, MMU, etc.
| c5 || c1 || 0 || Data auxiliary fault status || {{yes2}} Privileged || {{yes2}} Privileged || (Cortex only.)
{| class="wikitable"
|-
| c5 || c1 || 1 || Instruction auxiliary fault status || {{yes2}} Privileged || {{yes2}} Privileged || (Cortex only.)
|-
| c6 || c0 || 0 || Fault address (FAR) || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c6 || c0 || 1 || Watchpoint fault address (W-FAR) || {{yes2}} Privileged || {{yes2}} Privileged || (ARM11 only.)
|-
| c6 || c0 || 2 || Instruction fault address (I-FAR) || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c7 || c0 || 4 || Wait for interrupt || {{no}} || {{yes2}} Privileged || (ARM11 only.)
|-
| c7 || c4 || 0 || Physical address (PA) || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c7 || c5 || 0 || Invalidate entire instruction cache || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c5 || 1 || Invalidate instruction line by modified virtual address (MVA) || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c5 || 2 || Invalidate instruction line by index || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c5 || 4 || Flush prefetch buffer || {{no}} || {{yes}} ||
|-
| c7 || c5 || 6 || Flush entire branch target cache || {{no}} || {{yes2}} Privileged || (ARM11 only.)
|-
| c7 || c5 || 7 || Flush branch target cache entry by MVA || {{no}} || {{yes2}} Privileged ||  (ARM11 only.)
|-
| c7 || c6 || 0 || Invalidate entire data cache || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c6 || 1 || Invalidate data cache line by MVA || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c6 || 2 || Invalidate data cache line by index || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c7 || 0 || Invalidate both caches || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c8 || 0 || VA to PA translation in the current world for privileged read permission || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c8 || 1 || VA to PA translation in the current world for privileged write permission || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c8 || 2 || VA to PA translation in the current world for user read permission || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c8 || 3 || VA to PA translation in the current world for user write permission || {{no}} || {{yes2}} Privileged ||  
|-
| c7 || c8 || 4 || VA to PA translation in the other world for privileged read permission || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c8 || 5 || VA to PA translation in the other world for privileged write permission || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c8 || 6 || VA to PA translation in the other world for user read permission || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c8 || 7 || VA to PA translation in the other world for user write permission || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c10 || 0 || Clean entire data cache || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c10 || 1 || Clean data cache line by MVA || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c10 || 2 || Clean data cache line by index || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c10 || 3 || Data synchronization barrier || {{no}} || {{yes}} || Ensure all outstanding explicit memory transactions complete before any following instructions begin.
|-
| c7 || c10 || 4 || Data memory barrier || {{no}} || {{yes}} || Ensure that all outstanding explicit memory transactions complete before any following explicit memory transactions begin.  
|-
| c7 || c10 || 5 || Cache dirty status || {{yes2}} Privileged || {{no}} ||
|-
| c7 || c13 || 1 || Prefetch instruction cache line || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c14 || 0 || Clean and invalidate entire data cache || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c14 || 1 || Clean and invalidate data cache line by MVA || {{no}} || {{yes2}} Privileged ||
|-
| c7 || c14 || 2 || Clean and invalidate data cache line by index || {{no}} || {{yes2}} Privileged ||
|-
| c8 || c5 || 0 || Invalidate instruction TLB unlocked entries || {{no}} || {{yes2}} Privileged ||
|-
| c8 || c5 || 1 || Invalidate instruction TLB entry by MVA || {{no}} || {{yes2}} Privileged ||
|-
| c8 || c5 || 2 || Invalidate instruction TLB entry on ASID match || {{no}} || {{yes2}} Privileged ||
|-
| c8 || c6 || 0 || Invalidate data TLB unlocked entries || {{no}} || {{yes2}} Privileged ||
|-
| c8 || c6 || 1 || Invalidate data TLB entry by MVA || {{no}} || {{yes2}} Privileged ||
|-
| c8 || c6 || 2 || Invalidate data TLB entry on ASID match || {{no}} || {{yes2}} Privileged ||
|-
| c8 || c7 || 0 || Invalidate unified TLB unlocked entries || {{no}} || {{yes2}} Privileged ||
|-
| c8 || c7 || 1 || Invalidate unified TLB entry by MVA || {{no}} || {{yes2}} Privileged ||
|-
| c8 || c7 || 2 || Invalidate unified TLB entry on ASID match || {{no}} || {{yes2}} Privileged ||
|-
| c9 || c0 || 0 || Data cache lockdown || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c9 || c0 || 1 || Instruction cache lockdown || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c9 || c1 || 0 || Data TCM region || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c9 || c1 || 1 || Instruction TCM region || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c9 || c1 || 2 || Data TCM non-secure control access || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c9 || c1 || 3 || Instruction TCM non-secure control access || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c9 || c2 || 0 || TCM selection || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c9 || c8 || 0 || Cache behavior override || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c10 || c0 || 0 || TLB lockdown || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c10 || c2 || 0 || Primary region memory remap register || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c10 || c2 || 1 || Normal region memory remap register || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
| c11 || c0 || 0 || DMA present || {{yes2}} Privileged || {{no}} ||
|-
| c11 || c0 || 1 || DMA queued || {{yes2}} Privileged || {{no}} ||
|-
| c11 || c0 || 2 || DMA running || {{yes2}} Privileged || {{no}} ||
|-
| c11 || c0 || 3 || DMA interrupting || {{yes2}} Privileged || {{no}} ||
|-
| c11 || c1 || 0 || DMA user accessibility || {{yes2}} Privileged || {{no}} ||
|-
| c11 || c2 || 0 || DMA channel number || {{yes}} || {{yes}} ||
|-
| c11 || c3 || 0 || DMA start || {{no}} || {{yes}} ||
|-
| c11 || c3 || 1 || DMA stop || {{no}} || {{yes}} ||
|-
| c11 || c3 || 2 || DMA clear || {{no}} || {{yes}} ||
|-
| c11 || c4 || 0 || DMA control || {{yes}} || {{yes}} ||  
|-
|-
! opcode2 !! Register || Comment
| c11 || c5 || 0 || DMA internal start address || {{yes}} || {{yes}} ||  
|-
|-
| 0 || Control register || The bits, from 0 to 31, control the followings (1 = on, 0 = off):
| c11 || c6 || 0 || DMA external start address || {{yes}} || {{yes}} ||  
* '''0 (M)''': MMU/Protection unit
* '''1 (A)''': Strict alignment
* '''2 (C)''': L1 data/unified cache
* '''3 (W)''': Write buffer
* '''7 (B)''': Big-endian (BE-32) vs little-endian.
* '''11 (Z)''': Program flow prediction.
* '''12 (I)''': L1 instruction cache.
* '''13 (V)''': High exception vectors (0xFFFFxxxx) vs low exception vectors (0x0000xxxx).
* '''14 (RR)''': Predictable replacement strategy.
* '''21 (FI)''': Fast interrupt (reduce latency), by disabling some performance features.
* '''22 (U)''': Unaligned loads and stores.
* '''23 (XP)''': ''Disable'' Subpage AP bits.
* '''25 (EE)''': Mixed Endian exception entry.
* '''26 (L2)''': L2 unified cache.
Implementation defined bits (10(F), 22(VE)), deprecated (8(S), 9(R), 15(L4)) and useless bits  (16(DT), 18(IT), 20(ST)) are not recorded here.
|-
|-
| 1 || Auxiliary control register ||  
| c11 || c7 || 0 || DMA internal end address || {{yes}} || {{yes}} ||  
|-
|-
| 2 || Coprocessor access register || In bits 2X...2X+1 (except X=14 and 15), defines the access right to coprocessor X. 0 = Deny, 1 = Kernel only, 3 = Full access.
| c11 || c8 || 0 || DMA channel status || {{yes}} || {{no}} ||  
|}
 
=== N=c2: Translation table base for VMSA ===
{| class="wikitable"
|-
|-
! opcode2 !! Register || Comment
| c11 || c15 || 0 || DMA context ID || {{yes2}} Privileged || {{yes2}} Privileged ||  
|-
|-
| 0 || Translation Table Base 0 (TTBR0) ||  
| c12 || c0 || 0 || Secure or non-secure vector base address || {{yes2}} Privileged || {{yes2}} Privileged ||  
|-
|-
| 1 || Translation Table Base 0 (TTBR1) ||
| c12 || c0 || 1 || Monitor vector base address || {{yes2}} Privileged || {{yes2}} Privileged ||  
|-
|-
| 2 || Translation Table Base Control ||
| c12 || c1 || 0 || Interrupt status || {{yes2}} Privileged || {{no}} ||  
|}
 
=== N=c3: Domain access control for MMU ===
In bits 2X...2X+1, defines the access right to domain X.
 
=== N=c5: Fault status for VMSA ===
Bits 0...3, 10 contains the abort status, 4...7 for the domain of abort and 11 for whether it's a read-abort (0) or write-abort (1).
 
{| class="wikitable"
|-
|-
! opcode2 !! Register || Comment
| c13 || c0 || 0 || Fast context switch extension (FSCE) PID || {{yes2}} Privileged || {{yes2}} Privileged || Deprecated.
|-
|-
| 0 || Combined/Data FSR ||
| c13 || c0 || 1 || Context ID || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
|-
| 1 || Instruction FSR ||
| c13 || c0 || 2 || User read/write thread and process ID || {{yes}} || {{yes}} ||
|}
 
=== N=c6: Fault address register for VMSA ===
{| class="wikitable"
|-
|-
! opcode2 !! Register || Comment
| c13 || c0 || 3 || User read-only thread and process ID || {{yes}} || {{yes2}} Privileged || Used to implement <tt>pthread_self()</tt> in the iPhoneOS.
|-
|-
| 0 || Combined/Data FAR ||
| c13 || c0 || 4 || Privileged only thread and process ID || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
|-
| 1 || Watchpoint FAR (WFAR) ||
| c15 || c2 || 4 || Peripheral port memory remap || {{yes2}} Privileged || {{yes2}} Privileged ||
|-
|-
| 2 || Instruction FAR (IFAR) ||
| c15 || c9 || 0 || Secure user and non-secure access validation control || {{yes2}} Privileged || {{yes2}} Privileged ||
|}
 
=== N=c7: Cache management functions ===
Not to be included here.
 
=== N=c8: TLB functions ===
Not to be included here.
 
=== N=c9: Cache lockdown functions ===
Not to be included here.
 
=== N=c10: TLB lockdown ===
Not to be included here.
 
=== N=c13: Process ID ===
This register can determine the current running thread.
{| class="wikitable"
|-
|-
! opcode2 !! Register || Comment
| c15 || c12 || 0 || Performance monitor control || {{yes}} || {{yes}} ||
|-
|-
| 0 || Fast Context Switch Extension (FCSE) PID || Deprecated
| c15 || c12 || 1 || Cycle counter || {{yes}} || {{yes}} ||
|-
|-
| 1 || Context ID || Bits 0...7 are the currently running Application Space Identifier (ASID). The rest are for the general purpose ID.
| c15 || c12 || 2 || Count 0 || {{yes}} || {{yes}} ||
|-
|-
| 3 || ? || Used in <tt>pthread</tt> to get the current thread<ref>http://opensource.apple.com/source/Libc/Libc-583/arm/pthreads/pthread_self.s</ref>.
| c15 || c12 || 3 || Count 1 || {{yes}} || {{yes}} ||
|}
|}


For example, the implementation of <tt>pthread_self</tt> in ARMv6 is
c15 is also involved in other operations using opcode 1 and above which are not reproduced here.
<source lang="asm">
_pthread_self:
mrc p15, 0, r0, c13, c0, 3
bx lr
</source>


== CP14: Debug Register ==
== CP14: Debug Register ==
Not to be included here.
Not to be included here.
== CP10 & CP11: Vector floating point coprocessor ==
Both CP10 and CP11 are used for the VFP11 coprocessor. CP10 is for single-precision and CP11 for double-precision.


== References ==
== References ==
<references/>
<references/>

Revision as of 18:42, 19 December 2009

This page describes various instructions associated to coprocessors on the ARM chip. [1]

CP15: System Control Coprocessor

Most operations are done using opcode "0". To read data from the coprocessor to the register rD, use the assembly

mcr p15, 0, <rD>, <cN>, <cM>, <opcode2>

To write data into coprocessor from rS, so

mrc p15, 0, <rS>, <cN>, <cM>, <opcode2>

Notable usage

In the iPhoneOS user-land, the most prominent use of CP15 is to provide thread-local storage via the "User read-only thread and process ID" register. For instance, in libSystem.dylib, pthread_self() is implemented as

_pthread_self:
	mrc	p15, 0, r0, c13, c0, 3
	bx	lr

Register allocation for Opcode 0

cN cM opcode2 Register Readable (mcr) Writable (mrc) Comments
c0 c0 0 Main ID Privileged No Contains vendor, architecture, part number, etc.[2]
c0 c0 1 Cache type Privileged No Size and architecture of cache.[3]
c0 c0 2 Tightly coupled memory (TCM) status Privileged No
c0 c0 3 Translation look-aside buffer (TLB) type Privileged No
c0 c0 5 Multiprocessor ID Privileged No (Cortex only.)
c0 c1 0 Processor feature 0 Privileged No
c0 c1 1 Processor feature 1 Privileged No
c0 c1 2 Debug feature 0 Privileged No
c0 c1 3 Auxiliary feature 0 Privileged No
c0 c1 4 Memory model feature 0 Privileged No
c0 c1 5 Memory model feature 1 Privileged No
c0 c1 6 Memory model feature 2 Privileged No
c0 c1 7 Memory model feature 3 Privileged No
c0 c2 0 Instruction set features 0 Privileged No
c0 c2 1 Instruction set features 1 Privileged No
c0 c2 2 Instruction set features 2 Privileged No
c0 c2 3 Instruction set features 3 Privileged No
c0 c2 4 Instruction set features 4 Privileged No
c1 c0 0 Control Privileged Privileged Controls whether MMU, cache, etc. are enabled or not.
c1 c0 1 Auxiliary control Privileged Privileged
c1 c0 2 Coprocessor access control Privileged Privileged
c1 c1 0 Secure configuration Privileged Privileged
c1 c1 1 Secure debug enable Privileged Privileged
c1 c1 2 Non-secure access control Privileged Privileged
c2 c0 0 Translation table base 0 (TTBR0) Privileged Privileged
c2 c0 1 Translation table base 1 (TTBR1) Privileged Privileged
c2 c0 2 Translation table base control Privileged Privileged
c3 c0 0 Domain access control Privileged Privileged
c5 c0 0 Data fault status (D-FSR) Privileged Privileged
c5 c0 1 Instruction fault status (I-FSR) Privileged Privileged
c5 c1 0 Data auxiliary fault status Privileged Privileged (Cortex only.)
c5 c1 1 Instruction auxiliary fault status Privileged Privileged (Cortex only.)
c6 c0 0 Fault address (FAR) Privileged Privileged
c6 c0 1 Watchpoint fault address (W-FAR) Privileged Privileged (ARM11 only.)
c6 c0 2 Instruction fault address (I-FAR) Privileged Privileged
c7 c0 4 Wait for interrupt No Privileged (ARM11 only.)
c7 c4 0 Physical address (PA) Privileged Privileged
c7 c5 0 Invalidate entire instruction cache No Privileged
c7 c5 1 Invalidate instruction line by modified virtual address (MVA) No Privileged
c7 c5 2 Invalidate instruction line by index No Privileged
c7 c5 4 Flush prefetch buffer No Yes
c7 c5 6 Flush entire branch target cache No Privileged (ARM11 only.)
c7 c5 7 Flush branch target cache entry by MVA No Privileged (ARM11 only.)
c7 c6 0 Invalidate entire data cache No Privileged
c7 c6 1 Invalidate data cache line by MVA No Privileged
c7 c6 2 Invalidate data cache line by index No Privileged
c7 c7 0 Invalidate both caches No Privileged
c7 c8 0 VA to PA translation in the current world for privileged read permission No Privileged
c7 c8 1 VA to PA translation in the current world for privileged write permission No Privileged
c7 c8 2 VA to PA translation in the current world for user read permission No Privileged
c7 c8 3 VA to PA translation in the current world for user write permission No Privileged
c7 c8 4 VA to PA translation in the other world for privileged read permission No Privileged
c7 c8 5 VA to PA translation in the other world for privileged write permission No Privileged
c7 c8 6 VA to PA translation in the other world for user read permission No Privileged
c7 c8 7 VA to PA translation in the other world for user write permission No Privileged
c7 c10 0 Clean entire data cache No Privileged
c7 c10 1 Clean data cache line by MVA No Privileged
c7 c10 2 Clean data cache line by index No Privileged
c7 c10 3 Data synchronization barrier No Yes Ensure all outstanding explicit memory transactions complete before any following instructions begin.
c7 c10 4 Data memory barrier No Yes Ensure that all outstanding explicit memory transactions complete before any following explicit memory transactions begin.
c7 c10 5 Cache dirty status Privileged No
c7 c13 1 Prefetch instruction cache line No Privileged
c7 c14 0 Clean and invalidate entire data cache No Privileged
c7 c14 1 Clean and invalidate data cache line by MVA No Privileged
c7 c14 2 Clean and invalidate data cache line by index No Privileged
c8 c5 0 Invalidate instruction TLB unlocked entries No Privileged
c8 c5 1 Invalidate instruction TLB entry by MVA No Privileged
c8 c5 2 Invalidate instruction TLB entry on ASID match No Privileged
c8 c6 0 Invalidate data TLB unlocked entries No Privileged
c8 c6 1 Invalidate data TLB entry by MVA No Privileged
c8 c6 2 Invalidate data TLB entry on ASID match No Privileged
c8 c7 0 Invalidate unified TLB unlocked entries No Privileged
c8 c7 1 Invalidate unified TLB entry by MVA No Privileged
c8 c7 2 Invalidate unified TLB entry on ASID match No Privileged
c9 c0 0 Data cache lockdown Privileged Privileged
c9 c0 1 Instruction cache lockdown Privileged Privileged
c9 c1 0 Data TCM region Privileged Privileged
c9 c1 1 Instruction TCM region Privileged Privileged
c9 c1 2 Data TCM non-secure control access Privileged Privileged
c9 c1 3 Instruction TCM non-secure control access Privileged Privileged
c9 c2 0 TCM selection Privileged Privileged
c9 c8 0 Cache behavior override Privileged Privileged
c10 c0 0 TLB lockdown Privileged Privileged
c10 c2 0 Primary region memory remap register Privileged Privileged
c10 c2 1 Normal region memory remap register Privileged Privileged
c11 c0 0 DMA present Privileged No
c11 c0 1 DMA queued Privileged No
c11 c0 2 DMA running Privileged No
c11 c0 3 DMA interrupting Privileged No
c11 c1 0 DMA user accessibility Privileged No
c11 c2 0 DMA channel number Yes Yes
c11 c3 0 DMA start No Yes
c11 c3 1 DMA stop No Yes
c11 c3 2 DMA clear No Yes
c11 c4 0 DMA control Yes Yes
c11 c5 0 DMA internal start address Yes Yes
c11 c6 0 DMA external start address Yes Yes
c11 c7 0 DMA internal end address Yes Yes
c11 c8 0 DMA channel status Yes No
c11 c15 0 DMA context ID Privileged Privileged
c12 c0 0 Secure or non-secure vector base address Privileged Privileged
c12 c0 1 Monitor vector base address Privileged Privileged
c12 c1 0 Interrupt status Privileged No
c13 c0 0 Fast context switch extension (FSCE) PID Privileged Privileged Deprecated.
c13 c0 1 Context ID Privileged Privileged
c13 c0 2 User read/write thread and process ID Yes Yes
c13 c0 3 User read-only thread and process ID Yes Privileged Used to implement pthread_self() in the iPhoneOS.
c13 c0 4 Privileged only thread and process ID Privileged Privileged
c15 c2 4 Peripheral port memory remap Privileged Privileged
c15 c9 0 Secure user and non-secure access validation control Privileged Privileged
c15 c12 0 Performance monitor control Yes Yes
c15 c12 1 Cycle counter Yes Yes
c15 c12 2 Count 0 Yes Yes
c15 c12 3 Count 1 Yes Yes

c15 is also involved in other operations using opcode 1 and above which are not reproduced here.

CP14: Debug Register

Not to be included here.

CP10 & CP11: Vector floating point coprocessor

Both CP10 and CP11 are used for the VFP11 coprocessor. CP10 is for single-precision and CP11 for double-precision.


References