Coprocessors

This page describes various instructions associated to coprocessors on the ARM chip.

CP15: System Control Coprocessor

Only Opcode 0 is described in the ARM-ARM. To copy data from the coprocessor to the register rD, use the assembly

mcr p15, 0, <rD>, <cN>, c0, <opcode2>
mrc p15, 0, <rS>, <cN>, c0, <opcode2>

N=c0: ID codes

ID codes are used to obtain information about the chip, e.g. the vendor, the cache size, etc. These values are all, naturally, read-only (only mcr should be used).

opcode2	Register	Comment
0	Main ID register	Gives information of the vendor, architecture, part number and revision.
1	Cache type register	Gives information of the cache type and size.
2	Tightly Coupled Memory (TCM) type register
3	TLB type register
4	Memory Protection Unit (MPU) type register

N=c1: Control registers

Configure for the cache, MMU, etc.

opcode2	Register	Comment
0	Control register	The bits, from 0 to 31, control the followings (1 = on, 0 = off): 0 (M): MMU/Protection unit 1 (A): Strict alignment 2 (C): L1 data/unified cache 3 (W): Write buffer 7 (B): Big-endian (BE-32) vs little-endian. 11 (Z): Program flow prediction. 12 (I): L1 instruction cache. 13 (V): High exception vectors (0xFFFFxxxx) vs low exception vectors (0x0000xxxx). 14 (RR): Predictable replacement strategy. 21 (FI): Fast interrupt (reduce latency), by disabling some performance features. 22 (U): Unaligned loads and stores. 23 (XP): Disable Subpage AP bits. 25 (EE): Mixed Endian exception entry. 26 (L2): L2 unified cache. Implementation defined bits (10(F), 22(VE)), deprecated (8(S), 9(R), 15(L4)) and useless bits (16(DT), 18(IT), 20(ST)) are not recorded here.
1	Auxiliary control register
2	Coprocessor access register	In bits 2X...2X+1 (except X=14 and 15), defines the access right to coprocessor X. 0 = Deny, 1 = Kernel only, 3 = Full access.

N=c2: Translation table base for VMSA

opcode2	Register	Comment
0	Translation Table Base 0 (TTBR0)
1	Translation Table Base 0 (TTBR1)
2	Translation Table Base Control

N=c3: Domain access control for MMU

In bits 2X...2X+1, defines the access right to domain X.

N=c5: Fault status for VMSA

Bits 0...3, 10 contains the abort status, 4...7 for the domain of abort and 11 for whether it's a read-abort (0) or write-abort (1).

opcode2	Register	Comment
0	Combined/Data FSR
1	Instruction FSR

N=c6: Fault address register for VMSA

opcode2	Register	Comment
0	Combined/Data FAR
1	Watchpoint FAR (WFAR)
2	Instruction FAR (IFAR)

N=c7: Cache management functions

Not to be included here.

N=c8: TLB functions

Not to be included here.

N=c9: Cache lockdown functions

Not to be included here.

N=c10: TLB lockdown

Not to be included here.

N=c13: Process ID

This register can determine the current running thread.

opcode2	Register	Comment
0	Fast Context Switch Extension (FCSE) PID	Deprecated
1	Context ID	Bits 0...7 are the currently running Application Space Identifier (ASID). The rest are for the general purpose ID.
3	?	Used in pthread to get the current thread.

For example, the implementation of pthread_self in ARMv6 is

_pthread_self:
	mrc	p15, 0, r0, c13, c0, 3
	bx	lr

CP14: Debug Register

Not to be included here.