Coprocessors

This page describes various instructions associated to coprocessors on the ARM chip.

CP15: System Control Coprocessor

Most operations are done using opcode "0". To read data from the coprocessor to the register rD, use the assembly

mrc p15, 0, <rD>, <cN>, <cM>, <opcode2>

To write data into coprocessor from rS, so

mcr p15, 0, <rS>, <cN>, <cM>, <opcode2>

Notable usage

In the iPhoneOS user-land, the most prominent use of CP15 is to provide thread-local storage via the "User read-only thread and process ID" register. For instance, in libSystem.dylib, pthread_self() is implemented as

_pthread_self:
	mrc	p15, 0, r0, c13, c0, 3
	bx	lr

Register allocation for Opcode 0

cN	cM	opcode2	Register	Readable (mrc)	Writable (mcr)	Comments
c0	c0	0	Main ID	Privileged	No	Contains vendor, architecture, part number, etc.
c0	c0	1	Cache type	Privileged	No	Size and architecture of cache.
c0	c0	2	Tightly coupled memory (TCM) status	Privileged	No
c0	c0	3	Translation look-aside buffer (TLB) type	Privileged	No
c0	c0	5	Multiprocessor ID	Privileged	No	(Cortex only.)
c0	c1	0	Processor feature 0	Privileged	No
c0	c1	1	Processor feature 1	Privileged	No
c0	c1	2	Debug feature 0	Privileged	No
c0	c1	3	Auxiliary feature 0	Privileged	No
c0	c1	4	Memory model feature 0	Privileged	No
c0	c1	5	Memory model feature 1	Privileged	No
c0	c1	6	Memory model feature 2	Privileged	No
c0	c1	7	Memory model feature 3	Privileged	No
c0	c2	0	Instruction set features 0	Privileged	No
c0	c2	1	Instruction set features 1	Privileged	No
c0	c2	2	Instruction set features 2	Privileged	No
c0	c2	3	Instruction set features 3	Privileged	No
c0	c2	4	Instruction set features 4	Privileged	No
c1	c0	0	Control	Privileged	Privileged	Controls whether MMU, cache, etc. are enabled or not.
c1	c0	1	Auxiliary control	Privileged	Privileged
c1	c0	2	Coprocessor access control	Privileged	Privileged
c1	c1	0	Secure configuration	Privileged	Privileged
c1	c1	1	Secure debug enable	Privileged	Privileged
c1	c1	2	Non-secure access control	Privileged	Privileged
c2	c0	0	Translation table base 0 (TTBR0)	Privileged	Privileged
c2	c0	1	Translation table base 1 (TTBR1)	Privileged	Privileged
c2	c0	2	Translation table base control	Privileged	Privileged
c3	c0	0	Domain access control	Privileged	Privileged
c5	c0	0	Data fault status (D-FSR)	Privileged	Privileged
c5	c0	1	Instruction fault status (I-FSR)	Privileged	Privileged
c5	c1	0	Data auxiliary fault status	Privileged	Privileged	(Cortex only.)
c5	c1	1	Instruction auxiliary fault status	Privileged	Privileged	(Cortex only.)
c6	c0	0	Fault address (FAR)	Privileged	Privileged
c6	c0	1	Watchpoint fault address (W-FAR)	Privileged	Privileged	(ARM11 only.)
c6	c0	2	Instruction fault address (I-FAR)	Privileged	Privileged
c7	c0	4	Wait for interrupt	No	Privileged	(ARM11 only.)
c7	c4	0	Physical address (PA)	Privileged	Privileged
c7	c5	0	Invalidate entire instruction cache	No	Privileged
c7	c5	1	Invalidate instruction line by modified virtual address (MVA)	No	Privileged
c7	c5	2	Invalidate instruction line by index	No	Privileged
c7	c5	4	Flush prefetch buffer	No	Yes
c7	c5	6	Flush entire branch target cache	No	Privileged	(ARM11 only.)
c7	c5	7	Flush branch target cache entry by MVA	No	Privileged	(ARM11 only.)
c7	c6	0	Invalidate entire data cache	No	Privileged
c7	c6	1	Invalidate data cache line by MVA	No	Privileged
c7	c6	2	Invalidate data cache line by index	No	Privileged
c7	c7	0	Invalidate both caches	No	Privileged
c7	c8	0	VA to PA translation in the current world for privileged read permission	No	Privileged
c7	c8	1	VA to PA translation in the current world for privileged write permission	No	Privileged
c7	c8	2	VA to PA translation in the current world for user read permission	No	Privileged
c7	c8	3	VA to PA translation in the current world for user write permission	No	Privileged
c7	c8	4	VA to PA translation in the other world for privileged read permission	No	Privileged
c7	c8	5	VA to PA translation in the other world for privileged write permission	No	Privileged
c7	c8	6	VA to PA translation in the other world for user read permission	No	Privileged
c7	c8	7	VA to PA translation in the other world for user write permission	No	Privileged
c7	c10	0	Clean entire data cache	No	Privileged
c7	c10	1	Clean data cache line by MVA	No	Privileged
c7	c10	2	Clean data cache line by index	No	Privileged
c7	c10	3	Data synchronization barrier	No	Yes	Ensure all outstanding explicit memory transactions complete before any following instructions begin.
c7	c10	4	Data memory barrier	No	Yes	Ensure that all outstanding explicit memory transactions complete before any following explicit memory transactions begin.
c7	c10	5	Cache dirty status	Privileged	No
c7	c13	1	Prefetch instruction cache line	No	Privileged
c7	c14	0	Clean and invalidate entire data cache	No	Privileged
c7	c14	1	Clean and invalidate data cache line by MVA	No	Privileged
c7	c14	2	Clean and invalidate data cache line by index	No	Privileged
c8	c5	0	Invalidate instruction TLB unlocked entries	No	Privileged
c8	c5	1	Invalidate instruction TLB entry by MVA	No	Privileged
c8	c5	2	Invalidate instruction TLB entry on ASID match	No	Privileged
c8	c6	0	Invalidate data TLB unlocked entries	No	Privileged
c8	c6	1	Invalidate data TLB entry by MVA	No	Privileged
c8	c6	2	Invalidate data TLB entry on ASID match	No	Privileged
c8	c7	0	Invalidate unified TLB unlocked entries	No	Privileged
c8	c7	1	Invalidate unified TLB entry by MVA	No	Privileged
c8	c7	2	Invalidate unified TLB entry on ASID match	No	Privileged
c9	c0	0	Data cache lockdown	Privileged	Privileged
c9	c0	1	Instruction cache lockdown	Privileged	Privileged
c9	c1	0	Data TCM region	Privileged	Privileged
c9	c1	1	Instruction TCM region	Privileged	Privileged
c9	c1	2	Data TCM non-secure control access	Privileged	Privileged
c9	c1	3	Instruction TCM non-secure control access	Privileged	Privileged
c9	c2	0	TCM selection	Privileged	Privileged
c9	c8	0	Cache behavior override	Privileged	Privileged
c10	c0	0	TLB lockdown	Privileged	Privileged
c10	c2	0	Primary region memory remap register	Privileged	Privileged
c10	c2	1	Normal region memory remap register	Privileged	Privileged
c11	c0	0	DMA present	Privileged	No
c11	c0	1	DMA queued	Privileged	No
c11	c0	2	DMA running	Privileged	No
c11	c0	3	DMA interrupting	Privileged	No
c11	c1	0	DMA user accessibility	Privileged	No
c11	c2	0	DMA channel number	Yes	Yes
c11	c3	0	DMA start	No	Yes
c11	c3	1	DMA stop	No	Yes
c11	c3	2	DMA clear	No	Yes
c11	c4	0	DMA control	Yes	Yes
c11	c5	0	DMA internal start address	Yes	Yes
c11	c6	0	DMA external start address	Yes	Yes
c11	c7	0	DMA internal end address	Yes	Yes
c11	c8	0	DMA channel status	Yes	No
c11	c15	0	DMA context ID	Privileged	Privileged
c12	c0	0	Secure or non-secure vector base address	Privileged	Privileged
c12	c0	1	Monitor vector base address	Privileged	Privileged
c12	c1	0	Interrupt status	Privileged	No
c13	c0	0	Fast context switch extension (FSCE) PID	Privileged	Privileged	Deprecated.
c13	c0	1	Context ID	Privileged	Privileged
c13	c0	2	User read/write thread and process ID	Yes	Yes
c13	c0	3	User read-only thread and process ID	Yes	Privileged	Used to implement pthread_self() in the iPhoneOS.
c13	c0	4	Privileged only thread and process ID	Privileged	Privileged
c15	c2	4	Peripheral port memory remap	Privileged	Privileged
c15	c9	0	Secure user and non-secure access validation control	Privileged	Privileged
c15	c12	0	Performance monitor control	Yes	Yes
c15	c12	1	Cycle counter	Yes	Yes
c15	c12	2	Count 0	Yes	Yes
c15	c12	3	Count 1	Yes	Yes

c15 is also involved in other operations using opcode 1 and above which are not reproduced here.

CP14: Debug Register

Not to be included here.

CP10 & CP11: Vector floating point coprocessor

Both CP10 and CP11 are used for the VFP11 coprocessor. CP10 is for single-precision and CP11 for double-precision.